Pad Placement and DC Guidelines
After applying the equation above, apply one of the equations in
Table 10–11, depending on the package type.
Table 10–11. Bidirectional Pad Limitation Formulas (Multiple VREF Inputs
and Outputs)
Package Type
Formula
FineLine BGA
(Total number of bidirectional pads) + (Total number of
output pads) ≤9 (per VCCIO/GNDpair)
QFP
Total number of bidirectional pads + Total number of output
pads ≤5 (per VCCIO/GNDpair)
Each I/O bank can only be set to a single VCCIO voltage level and a single
VREF voltage level at a given time. Pins of different I/O standards can
share the bank if they have compatible VCCIO values (refer to Table 10–4
for more details) and compatible VREF voltage levels.
DDR and QDR Pads
For dedicated DQ and DQS pads on a DDR interface, DQ pads have to be
on the same power bank as DQS pads. With the DDR and DDR2 memory
interfaces, a VCCIOand ground pair can have a maximum of five DQ
pads.
For a QDR interface, D is the QDR output and Q is the QDR input. D pads
and Q pads have to be on the same power bank as CQ. With the QDR and
QDRII memory interfaces, a VCCIOand ground pair can have a
maximum of five D and Q pads.
By default, the Quartus II software assigns D and Q pads as regular I/O
pins. If you do not specify the function of a D or Q pad in the Quartus II
software, the software sets them as regular I/O pins. If this occurs,
Cyclone II QDR and QDRII performance is not guaranteed.
DC Guidelines
There is a current limit of 240 mA per eight consecutive output top and
bottom pins per power pair, as shown by the following equation:
pin+7
Σ IPIN < 240mA per power pair
pin
There is a current limit of 240 mA per 12 consecutive output side (left and
right) pins per power pair, as shown by the following equation:
10–32
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
ALTERA [ ALTERA CORPORATION ]
