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EP2C20F256C8N 参数 Datasheet PDF下载

EP2C20F256C8N图片预览
型号: EP2C20F256C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 可编程逻辑PC时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Termination  
The majority of the Cyclone II I/O standards are single-ended,  
non-voltage-referenced I/O standards and, as such, the following I/O  
standards do not specify a recommended termination scheme:  
I/O Termination  
3.3-V LVTTL and LVCMOS  
2.5-V LVTTL and LVCMOS  
1.8-V LVTTL and LVCMOS  
1.5-V LVCMOS  
3.3-V PCI and PCI-X  
Voltage-Referenced I/O Standard Termination  
Voltage-referenced I/O standards require both an input reference  
voltage, VREF, and a termination voltage, VTT. The reference voltage of the  
receiving device tracks the termination voltage of the transmitting device.  
For more information on termination for voltage-referenced I/O  
standards, refer to “Supported I/O Standards” on page 10–1.  
Differential I/O Standard Termination  
Differential I/O standards typically require a termination resistor  
between the two signals at the receiver. The termination resistor must  
match the differential load impedance of the bus.  
Cyclone II devices support differential I/O standards LVDS, RSDS, and  
mini-LVDS, and differential LVPECL.  
For more information on termination for differential I/O standards, refer  
to “Supported I/O Standards” on page 10–1.  
10–26  
Altera Corporation  
Cyclone II Device Handbook, Volume 1  
February 2008  
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