Supported I/O Standards
Table 10–3. Cyclone II 33-MHz PCI Support (Part 2 of 2)
–6, –7 and –8 Speed Grades
Device
Package
64 Bits
—
32 Bits
v
EP2C20
240-pin PQFP
256-pin FineLine BGA
484-pin FineLine BGA
484-pin FineLine BGA
672-pin FineLine BGA
484-pin FineLine BGA
672-pin FineLine BGA
672-pin FineLine BGA
896-pin FineLine BGA
—
v
v
v
v
v
v
v
v
v
EP2C35
EP2C50
EP2C70
v
v
v
v
v
v
3.3-V PCI-X
The 3.3-V PCI-X I/O standard is formulated under PCI-X Local Bus
Specification Revision 1.0 developed by the PCI SIG.
The PCI-X 1.0 standard is used for applications that interface to the PCI
local bus. The standard enables the design of systems and devices that
operate at clock speeds up to 133 MHz, or 1 gigabit per second (Gbps) for
a 64-bit bus. The PCI-X 1.0 protocol enhancements enable devices to
operate much more efficiently, providing more usable bandwidth at any
clock frequency. By using the PCI-X 1.0 standard, devices can be designed
to meet PCI-X 1.0 requirements and operate as conventional 33- and
66-MHz PCI devices when installed in those systems. This standard
requires 3.3-V VCCIO. Cyclone II devices are fully compliant with the 3.3-V
PCI-X Specification Revision 1.0a and meet the 133 MHz operating
frequency and timing requirements. The 3.3-V PCI-X standard does not
require input reference voltages or board terminations. Cyclone II devices
support both input and output levels operation for left and right I/O
banks.
Easy-to-Use, Low-Cost PCI Express Solution
PCI Express is rapidly establishing itself as the successor to PCI,
providing higher performance, increased flexibility, and scalability for
next-generation systems without increasing costs, all while maintaining
software compatibility with existing PCI applications. Now you can
easily design high volume, low-cost PCI Express ×1 solutions today
featuring:
10–6
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
ALTERA [ ALTERA CORPORATION ]
