Supported I/O Standards
3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B)
The 3.3-V LVCMOS I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVCMOS standard defines the
DC interface parameters for digital circuits operating from a 3.0- or 3.3-V
power supply and driving or being driven by LVCMOS-compatible
devices.
The LVCMOS standard specifies the same input voltage requirements as
LVTTL (– 0.3 V ≤VI ≤3.9 V). The output buffer drives to the rail to meet the
minimum high-level output voltage requirements. The 3.3-V I/O
standard does not require input reference voltages or board terminations.
Cyclone II devices support both input and output levels specified by the
3.3-V LVCMOS I/O standard.
3.3-V (PCI Special Interest Group [SIG] PCI Local Bus
Specification Revision 3.0)
The PCI local bus specification is used for applications that interface to
the PCI local bus, which provides a processor-independent data path
between highly integrated peripheral controller components, peripheral
add-in boards, and processor/memory systems. The conventional PCI
specification revision 3.0 defines the PCI hardware environment
including the protocol, electrical, mechanical, and configuration
specifications for the PCI devices and expansion boards. This standard
requires a 3.3-V VCCIO. The 3.3-V PCI standard does not require input
reference voltages or board terminations.
The side (left and right) I/O banks on all Cyclone II devices are fully
compliant with the 3.3V PCI Local Bus Specification Revision 3.0 and
meet 32-bit/66 MHz operating frequency and timing requirements.
Table 10–2 lists the specific Cyclone II devices that support 64- and 32-bit
PCI at 66 MHz.
Table 10–2. Cyclone II 66-MHz PCI Support (Part 1 of 2)
–6 and –7 Speed Grades
Device
Package
64 Bits
32 Bits
EP2C5
144-pin TQFP
208-pin PQFP
v
v
256-pin FineLineBGA®
10–4
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
ALTERA [ ALTERA CORPORATION ]
