DDR Memory Interface Pins
Figure 9–10. Cyclone II DQS Postamble Circuitry Control Timing Waveform
DQS
DQS'
Reset
EnableN
DDR Input Registers
In Cyclone II devices, the DDR input registers are implemented with five
internal LE registers located in the logic array block (LAB) adjacent to the
DDR input pin (see Figure 9–11). The DDR data is fed to the first two
registers, input register AIand input register BI. Input register BI
captures the DDR data present during the rising edge of the clock. Input
register AI captures the DDR data present during the falling edge of the
clock. Register CIaligns the data before it is transferred to the
resynchronization registers.
Figure 9–11. DDR Input Implementation
DDR Input Configuration in Cyclone II
DQ
dataout_h
LE
Register
LE
Register
sync_reg_h
Input Register AI
neg_reg_out
dataout_l
LE
Register
LE
Register
LE
Register
Inverted &
Delayed DQS
Clock Delay
Control Circuitry
Input Register BI
sync_reg_l
Register CI
resynch_clk
DQS
t
9–18
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
