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EP2C20F256C8N 参数 Datasheet PDF下载

EP2C20F256C8N图片预览
型号: EP2C20F256C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 可编程逻辑PC时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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External Memory Interfaces  
Phase Lock Loop (PLL)  
When using the Cyclone II I/O banks to interface with the DDR memory,  
at least one PLL with two outputs is needed to generate the system clock  
and the write clock. The system clock generates the DQS write signals,  
commands, and addresses. The write clock shifts by –90° from the system  
clock and generates the DQ signals during writes.  
Clock Delay Control  
Clock delay control circuit on each DQS pin allows a phase shift that  
center-aligns the incoming DQS signals within the data window of their  
corresponding DQ data signals. The phase-shifted DQS signals drive the  
global clock network. This global DQS signal then clocks the DQ signals  
on internal LE registers. The clock delay control circuitry is used during  
the read operations where the DQS signals are acting as input clocks or  
strobes.  
Figure 9–8 illustrates DDR SDRAM interfacing from the I/O pins  
through the dedicated circuitry to the logic array.  
Figure 9–8. DDR SDRAM Interfacing  
DQS  
DQ  
LE  
Register  
LE  
Register  
OE  
OE  
t
Adjacent LAB LEs  
LE  
LE  
Register  
Register  
LE  
Register  
LE  
Register  
V
DataA  
DataB  
LE  
Register  
LE  
Register  
CC  
LE  
Register  
LE  
Register  
LE  
Register  
LE  
Register  
LE  
Register  
GND  
clk  
Clock Delay  
Control Circuitry  
PLL  
Global Clock  
en/dis  
-90˚ Shifted clk  
Resynchronizing  
to System Clock  
Clock Control  
Block  
Dynamic Enable/Disable  
Circuitry  
ENOUT  
ena_register_mode  
Figure 9–1 on page 9–4 shows an example where the DQS signal is shifted  
by 90°. The DQS signal goes through the 90° shift delay set by the clock  
delay control circuitry and global clock routing delay from the clock delay  
control circuitry to the DQ LE registers. The DQ signals only goes through  
routing delays from the DQ pin to the DQ LE registers. The delay from  
Altera Corporation  
February 2007  
9–15  
Cyclone II Device Handbook, Volume 1