PLLs in Cyclone II Devices
Figure 7–12. Cyclone II Clock Control Blocks Placement
Clock Control
Output from PLL
Input to PLL
Block
CLK[8..11]
4
PLL
3
PLL
2
3
GCLK[8..11]
Output from PLL
3
4
Clock Control
Block
GCLK[0..3]
GCLK[4..7]
CLK[0..3]
CLK[4..7]
Clock Control
Block
4
3
Output from PLL
GCLK[12..15]
PLL
1
PLL
4
3
4
CLK[12..15]
Clock Control
Block
Output from PLL
The inputs to the four clock control blocks on each side are chosen from
among the following clock sources:
■
■
■
Four clock input pins
Three PLL counter outputs
Two DPCLKpins and two CDPCLKpins from both the left and right
sides and four DPCLKpins and two CDPCLKpins from both the top
and bottom
■
Four signals from internal logic
Altera Corporation
February 2007
7–27
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
