Timing Model
Table 6–53. Stratix GX Global Clock External I/O Timing Parameters (Part 2 of 2)
Notes (1), (2)
Symbol
Parameter
Conditions
tINHPLL
Hold time for input or bidirectional pin using column IOE
input register with global clock fed by enhanced PLL with
default phase setting
tOUTCOPLL
Clock-to-output delay output or bidirectional pin using
column IOE output register with global clock enhanced PLL
with default phase setting
CLOAD = 10 pF
Notes to Table 6–53:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device,
speed grade, and the specific parameter in question. You should use the Quartus II software to verify the external
timing for any pin.
Tables 6–54 through 6–59 show the external timing parameters on column
and row pins for EP1SGX10 devices.
Table 6–54. EP1SGX10 Column Pin Fast Regional Clock External I/O Timing Parameters
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tINSU
tINH
tOUTCO
2.245
0.000
2.000
2.332
0.000
2.000
2.666
0.000
2.000
ns
ns
ns
4.597
4.920
5.635
Table 6–55. EP1SGX10 Column Pin Regional Clock External I/O Timing Parameters
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Symbol
Unit
Min
Max
4.728
2.629
Min
Max
5.078
2.769
Min
Max
6.004
3.158
tINSU
tINH
2.114
0.000
2.000
1.035
0.000
0.500
2.218
0.000
2.000
0.941
0.000
0.500
2.348
0.000
2.000
1.070
0.000
0.500
ns
ns
ns
ns
ns
ns
tOUTCO
tINSUPLL
tINHPLL
tOUTCOPLL
6–38
Altera Corporation
June 2006
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
