Operating Conditions
Table 6–6. Stratix GX Transceiver Block On-Chip Termination (Part 2 of 2)
Symbol
Parameter
Conditions
Min
Typ
Max Units
Refclkb Dedicated transceiver
clock termination
Commercial and industrial, 100-Ωsetting
Commercial and industrial, 120-Ωsetting
Commercial and industrial, 150-Ωsetting
103
120
149
108
128
158
113
134
167
Ω
Ω
Ω
Notes to Tables 6–1 through 6–6:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Conditions beyond those listed in Table 6–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns. (The information in this note does not include the
transceiver pins. See note 13 for information about the transient voltage on the transceiver pins.)
(4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5) VCCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses.
(6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(7) Typical values are for TA = 25° C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(8) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO
settings (3.3, 2.5, 1.8, and 1.5 V).
(9) Pin pull-up resistance values decrease if an external source drives the pin higher than VCCIO
.
(10) The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is
not violated.
(11) Each usable quad requires its own RREF resistor path to ground. For example, the “D” in the EP1SGX25DC1020
device code means it has two usable quad so two different RREF pins must be connected to a RREF resistor each to
ground. The DC signal on the RREF pin must be as clean as possible. Ensure that no noise is coupled to this pin.
(12) The Stratix GX device’s recommended operating conditions do not include the transceiver. Refer to Tables 6–4 to
6–7.
(13) Minimum DC input to the transceiver pins is –0.5 V. During transitions, the transceiver pins may undershoot to
–0.5 V or overshoot to 3.5 V for input currents less than 100 mA and periods shorter than 20 ns.
Table 6–7. Stratix GX Transceiver Block AC Specification (Part 1 of 7)
-6 Commercial &
Industrial Speed
Grade
-7 Commercial &
Industrial Speed
Grade
-5 Commercial
Speed Grade (1)
Symbol /
Description
Conditions
Unit
(1)
(1)
Min Typ
Max
Min Typ
Max
Min Typ
Max
Power per
quadrant
(PCS +
PMA)
3.125 Gbps, 400-
mV Vod
0 pre-emphasis
450
450
mW
6–4
Altera Corporation
June 2006
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
