Stratix GX Architecture
Input Registers
A bank of optional input registers is located at the input of each multiplier
and multiplicand inputs to the multiplier. When these registers are
configured for parallel data inputs, they are driven by regular routing
resources. You can use a clock signal, asynchronous clear signal, and a
clock enable signal to independently control each set of A and B inputs for
each multiplier in the DSP block. You select these control signals from a
set of four different clock[3..0], aclr[3..0], and ena[3..0]
signals that drive the entire DSP block.
You can also configure the input registers for a shift register application.
In this case, the input registers feed the multiplier and drive two
dedicated shift output lines: shiftoutAand shiftoutB. The shift
outputs of one multiplier block directly feed the adjacent multiplier block
in the same DSP block (or the next DSP block) as shown in Figure 4–32, to
form a shift register chain. This chain can terminate in any block, that is,
you can create any length of shift register chain up to 224 registers. You
can use the input shift registers for FIR filter applications. One set of shift
inputs can provide data for a filter, and the other are coefficients that are
optionally loaded in serial or parallel. When implementing 9 × 9- and 18
× 18-bit multipliers, you do not need to implement external shift registers
in LAB LEs. You implement all the filter circuitry within the DSP block
and its routing resources, saving LE and general routing resources for
general logic. External registers are needed for shift register inputs when
using 36 × 36-bit multipliers.
Altera Corporation
February 2005
4–53
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
