Stratix Architecture
Figure 2–33. Multiplier Sub-Blocks Using Input Shift Register Connections
Note (1)
Data A
D
Q
ENA
A[n] × B[n]
D
Q
CLRN
ENA
Data B
D
Q
CLRN
ENA
CLRN
Data B
Data A
D
Q
Q
ENA
A[n Ð 1] × B[n Ð 1]
D
Q
CLRN
ENA
D
CLRN
ENA
CLRN
Data A
Data B
D
Q
Q
ENA
A[n Ð 2] × B[n Ð 2]
D
Q
CLRN
ENA
D
CLRN
ENA
CLRN
Note to Figure 2–33:
(1) Either Data A or Data B input can be set to a parallel input for constant coefficient
multiplication.
Altera Corporation
July 2005
2–59
Stratix Device Handbook, Volume 1