DC & Switching Characteristics
Tables 4–109 and 4–110 show the adder delays for the column and row
IOE programmable delays. These delays are controlled with the
Quartus II software logic options listed in the Parameter column.
Table 4–109. Stratix IOE Programmable Delays on Column Pins Note (1)
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Setting
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Decrease input delay Off
to internal cells
3,970
3,390
2,810
224
224
3,900
0
4,367
3,729
3,091
235
235
4,290
0
5,022
4,288
3,554
270
270
4,933
0
5,908
5,045
4,181
318
318
5,804
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Small
Medium
Large
On
Decrease input delay Off
to input register
On
Decrease input delay Off
1,240
0
1,364
0
1,568
0
1,845
0
to output register
On
Increase delay to
output pin
Off
On
Off
On
0
0
0
0
397
0
417
0
417
0
417
0
Increase delay to
output enable pin
338
0
372
0
427
0
503
0
Increase output clock Off
enable delay
Small
540
1,016
1,016
0
594
1,118
1,118
0
683
1,285
1,285
0
804
1,512
1,512
0
Large
On
Increase input clock
enable delay
Off
Small
Large
On
540
1,016
1,016
0
594
1,118
1,118
0
683
1,285
1,285
0
804
1,512
1,512
0
Increase output
enable clock enable
delay
Off
Small
Large
On
540
1,016
1,016
0
594
1,118
1,118
0
683
1,285
1,285
0
804
1,512
1,512
0
Increase tZX delay to
output pin
Off
On
2,199
2,309
2,309
2,309
Altera Corporation
July 2005
4–73
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
