DC & Switching Characteristics
Table 4–107. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2)
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
3.3-V LVTTL
4 mA
8 mA
1,822
1,586
686
1,913
1,665
720
1,913
1,665
720
1,913
1,665
720
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
12 mA
16 mA
24 mA
2 mA
630
662
662
662
0
0
0
0
2.5-V LVTTL
2,925
1,496
937
3,071
1,571
984
3,071
1,571
984
3,071
1,571
984
8 mA
12 mA
16 mA
2 mA
1,003
7,101
3,620
3,109
10,941
7,431
5,990
–959
–438
660
1,053
7,456
3,801
3,265
11,488
7,803
6,290
–1,007
–460
693
1,053
7,456
3,801
3,265
11,488
7,803
6,290
–1,007
–460
693
1,053
7,456
3,801
3,265
11,488
7,803
6,290
–1,007
–460
693
1.8-V LVTTL
1.5-V LVTTL
8 mA
12 mA
2 mA
4 mA
8 mA
GTL
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
660
693
693
693
660
693
693
693
660
693
693
693
AGP 2×
288
303
303
303
CTT
631
663
663
663
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
301
316
316
316
–359
523
–377
549
–377
549
–377
549
–49
–51
–51
–51
2,315
723
2,431
759
2,431
759
2,431
759
1,687
1,095
599
1,771
1,150
629
1,771
1,150
678
1,771
1,150
744
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
87
102
102
102
Altera Corporation
July 2005
4–71
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
