DC & Switching Characteristics
the FPGA device. The Quartus II software calculates the I/O timing for
each I/O standard with a default baseline loading as specified by the I/O
standard.
Altera measures clock-to-output delays (tCO) at worst-case process,
minimum voltage, and maximum temperature (PVT) for the 3.3-V LVTTL
I/O standard with 24 mA (default case) current drive strength setting and
fast slew rate setting. I/O adder delays are measured to calculate the tCO
change at worst-case PVT across all I/O standards and current drive
strength settings with the default loading shown in Table 4–101 on
page 4–62. Timing derating data for additional loading is taken for tCO
across worst-case PVT for all I/O standards and drive strength settings.
These three pieces of data are used to predict the timing at the output pin.
tCO at pin = tOUTCO max for 3.3-V 24 mA LVTTL + I/O Adder +
Output Delay Adder for Loading
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1. Simulate the output driver of choice into the generalized test setup
using values from Table 4–101 on page 4–62.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS input buffer model or an equivalent
capacitance value to represent the load.
4. Record the time to VMEAS.
5. Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-input) of the PCB trace.
The Quartus II software reports maximum timing with the conditions
shown in Table 4–101 on page 4–62 using the proceeding equation.
Figure 4–7 on page 4–62 shows the model of the circuit that is represented
by the Quartus II output timing.
Altera Corporation
July 2005
4–61
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
