High-Speed Differential I/O Support
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed differential I/O
clocks to drive the SERDES block and/or external pin, and a low-speed
clock to drive the logic array.
The Quartus II MegaWizard® Plug-In Manager only allows the
implementation of up to 20 receiver or 20 transmitter channels for each
fast PLL. These channels operate at up to 840 Mbps. The receiver and
transmitter channels are interleaved such that each I/O bank on the left
and right side of the device has one receiver channel and one transmitter
channel per LAB row. Figure 2–74 shows the fast PLL and channel layout
in EP1S10, EP1S20, and EP1S25 devices. Figure 2–75 shows the fast PLL
and channel layout in the EP1S30 to EP1S80 devices.
Figure 2–74. Fast PLL & Channel Layout in the EP1S10, EP1S20 or EP1S25 Devices Note (1)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Transmitter
Transmitter
Receiver
Receiver
Fast
PLL 1
Fast
PLL 4
CLKIN
CLKIN
CLKIN
CLKIN
(3)
(3)
Fast
PLL 2
Fast
PLL 3
Transmitter
Receiver
Transmitter
Receiver
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Notes to Figure 2–74:
(1) Wire-bond packages support up to 624 Mbps.
(2) See Table 2–41 for the number of channels each device supports.
(3) There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for
“low” speed channels, as labeled in the device pin-outs at www.altera.com.
2–138
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
