High-Speed Differential I/O Support
Table 2–39. EP1S40 Differential Channels (Part 2 of 2) Note (1)
Maximum
Speed
(Mbps)
Center Fast PLLs
Corner Fast PLLs (2), (3)
Transmitter/
Receiver Channels
Total
Package
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
956-pin
BGA
Transmitter 80
(4)
840
18
35
20
40
17
35
20
40
17
35
20
40
18
35
20
40
20
20
18
18
20
20
20
17
17
20
20
20
17
17
20
20
20
18
18
20
840 (5)
840
Receiver
80
840 (5)
840
1,020-pin
FineLine
BGA
Transmitter 80 (10)
18
(2)
17
(3)
17
(3)
18
(2)
(4)
(7)
35
(5)
35
(5)
35
(5)
35
(5)
20
20
20
20
840 (5), (8)
Receiver
840
20
20
20
20
18
(2)
17
(3)
17
(3)
18 (2)
18 (2)
20
80 (10)
(7)
40
40
40
40
18
(2)
17
(3)
17
(3)
840 (5), (8)
1,508-pin
FineLine
BGA
Transmitter 80 (10)
(4)
840
18
(2)
17
(3)
17
(3)
18
(2)
20
20
20
(7)
35
(5)
35
(5)
35
(5)
35
(5)
20
20
20
20
840 (5), (8)
Receiver
80 (10)
(7)
840
20
20
20
20
18
(2)
17
(3)
17
(3)
18 (2)
18 (2)
40
40
40
40
18
(2)
17
(3)
17
(3)
840 (5), (8)
Table 2–40. EP1S60 Differential Channels (Part 1 of 2) Note (1)
Maximum
Speed
(Mbps)
Center Fast PLLs
Corner Fast PLLs (2), (3)
Transmitter/
Receiver Channels
Total
Package
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
956-pin
BGA
Transmitter 80
(4)
840
12
22
20
40
10
22
20
40
10
22
20
40
12
22
20
40
20
20
12
12
20
20
10
10
20
20
10
10
20
20
12
12
840 (5), (8)
840
Receiver
80
840 (5), (8)
2–134
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1