PLLs & Clock Networks
provide general purpose clocking with multiplication and phase shifting
as well as high-speed outputs for high-speed differential I/O support.
Enhanced and fast PLLs work together with the Stratix high-speed I/O
and advanced clock architecture to provide significant improvements in
system performance and bandwidth.
The Quartus II software enables the PLLs and their features without
requiring any external devices. Table 2–18 shows the PLLs available for
each Stratix device.
Table 2–18. Stratix Device PLL Availability
Fast PLLs
Enhanced PLLs
Device
1
2
3
4
7
8
9
10
5(1)
v
v
v
v
v
v
v
6(1) 11(2) 12(2)
EP1S10
EP1S20
EP1S25
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
EP1S30
EP1S40
EP1S60
EP1S80
v (3) v (3) v (3) v (3)
v (3) v (3) v (3) v (3)
v(3) v(3)
v
v
v
v
v
v
v
v
v
v
v
v
Notes to Table 2–18:
(1) PLLs 5 and 6 each have eight single-ended outputs or four differential outputs.
(2) PLLs 11 and 12 each have one single-ended output.
(3) EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA® package.
2–82
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
