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EP1S80B1508C7ES 参数 Datasheet PDF下载

EP1S80B1508C7ES图片预览
型号: EP1S80B1508C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix器件系列数据手册 [Stratix Device Family Data Sheet]
分类和应用:
文件页数/大小: 290 页 / 3583 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix Architecture  
Table 2–19 shows the enhanced PLL and fast PLL features in Stratix  
devices.  
Table 2–19. Stratix PLL Features  
Feature  
Enhanced PLL  
Fast PLL  
Clock multiplication and division  
Phase shift  
m/(n × post-scale counter) (1)  
m/(post-scale counter) (2)  
Down to 156.25-ps increments (3), (4) Down to 125-ps increments (3), (4)  
Delay shift  
250-ps increments for 3 ns  
Clock switchover  
v
v
v
v
PLL reconfiguration  
Programmable bandwidth  
Spread spectrum clocking  
Programmable duty cycle  
Number of internal clock outputs  
v
v
3 (5)  
(7)  
6
Number of external clock outputs Four differential/eight singled-ended  
or one single-ended (6)  
Number of feedback clock inputs  
2 (8)  
Notes to Table 2–19:  
(1) For enhanced PLLs, m, n, range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty  
cycle. With a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512.  
(2) For fast PLLs, m and post-scale counters range from 1 to 32.  
(3) The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.  
(4) For degree increments, Stratix devices can shift all output frequencies in increments of at least 45° . Smaller degree  
increments are possible depending on the frequency and divide parameters.  
(5) PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output ports per PLL.  
(6) Every Stratix device has two enhanced PLLs (PLLs 5 and 6) with either eight single-ended outputs or four  
differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1S80, EP1S60, and EP1S40 devices  
each have one single-ended output. Devices in the 780 pin FineLine BGA packages do not support PLLs 11 and 12.  
(7) Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data  
channel to generate txclkout.  
(8) Every Stratix device has two enhanced PLLs with one single-ended or differential external feedback input per PLL.  
Altera Corporation  
July 2005  
2–83  
Stratix Device Handbook, Volume 1  
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