Digital Signal Processing Block
Table 2–13 shows the number of DSP blocks in each Stratix device.
Table 2–13. DSP Blocks in Stratix Devices Notes (1), (2)
Total 9 × 9
Multipliers
Total 18 × 18 Total 36 × 36
Device
DSP Blocks
Multipliers
Multipliers
EP1S10
6
48
80
24
40
40
48
56
72
88
6
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
10
10
12
14
18
22
10
10
12
14
18
22
80
96
112
144
176
Notes to Table 2–13:
(1) Each device has either the number of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
(2) The number of supported multiply functions shown is based on signed/signed
or unsigned/unsigned implementations.
DSP block multipliers can optionally feed an adder/subtractor or
accumulator within the block depending on the configuration. This
makes routing to LEs easier, saves LE routing resources, and increases
performance, because all connections and blocks are within the DSP
block. Additionally, the DSP block input registers can efficiently
implement shift registers for FIR filter applications.
Figure 2–30 shows the top-level diagram of the DSP block configured for
18 × 18-bit multiplier mode. Figure 2–31 shows the 9 × 9-bit multiplier
configuration of the DSP block.
2–54
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
