Timing Model
Table 4–50. M-RAM Block Internal Timing Microparameters (Part 2 of 2)
-5
-6
-7
-8
Symbol
Unit
Min
25
18
25
18
25
18
25
18
25
18
Max
Min
25
20
25
20
25
20
25
20
25
20
Max
Min
28
23
28
23
28
23
28
23
28
23
Max
Min
33
27
33
27
33
27
33
27
33
27
Max
tMRAMBESU
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tMRAMBEH
tMRAMDATAASU
tMRAMDATAAH
tMRAMADDRASU
tMRAMADDRAH
tMRAMDATABSU
tMRAMDATABH
tMRAMADDRBSU
tMRAMADDRBH
tMRAMDATACO1
tMRAMDATACO2
tMRAMCLKHL
1,038
4,362
1,053
4,939
1,210
5,678
1,424
6,681
1,000
135
1,111
150
1,190
172
1,400
202
tMRAMCLR
Table 4–51. Routing Delay Internal Timing Parameters
-5 -6
-7
-8
Unit
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
tR4
268
295
339
390
461
676
641
840
647
455
ps
ps
ps
ps
ps
ps
ps
tR8
371
465
440
577
445
313
349
512
484
634
489
345
401
588
557
730
563
396
tR24
tC4
tC8
tC16
tLOCAL
Routing delays vary depending on the load on that specific routing line.
The Quartus II software reports the routing delay information when
running the timing analysis for a design.
4–32
Altera Corporation
Stratix Device Handbook, Volume 1
January 2006
ALTERA [ ALTERA CORPORATION ]
