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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Introduction  
Table 1–1. Stratix Device Features — EP1S10, EP1S20, EP1S25, EP1S30  
Feature  
EP1S10  
EP1S20  
EP1S25  
EP1S30  
LEs  
10,570  
18,460  
25,660  
32,470  
M512 RAM blocks (32 × 18 bits)  
M4K RAM blocks (128 × 36 bits)  
M-RAM blocks (4K × 144 bits)  
Total RAM bits  
94  
194  
224  
295  
60  
82  
138  
171  
1
2
2
4
3,317,184  
12  
920,448  
1,669,248  
1,944,576  
DSP blocks  
6
48  
6
10  
80  
6
10  
80  
6
Embedded multipliers (1)  
PLLs  
96  
10  
Maximum user I/O pins  
426  
586  
706  
726  
Table 1–2. Stratix Device Features — EP1S40, EP1S60, EP1S80  
Feature  
EP1S40  
EP1S60  
EP1S80  
LEs  
41,250  
384  
57,120  
574  
79,040  
767  
M512 RAM blocks (32 × 18 bits)  
M4K RAM blocks (128 × 36 bits)  
M-RAM blocks (4K × 144 bits)  
Total RAM bits  
183  
292  
364  
4
6
9
3,423,744  
14  
5,215,104  
18  
7,427,520  
22  
DSP blocks  
Embedded multipliers (1)  
PLLs  
112  
144  
176  
12  
12  
12  
Maximum user I/O pins  
822  
1,022  
1,238  
Note to Tables 1–1 and 1–2:  
(1) This parameter lists the total number of 9 × 9-bit multipliers for each device. For the total number of 18 × 18-bit  
multipliers per device, divide the total number of 9 × 9-bit multipliers by 2. For the total number of 36 × 36-bit  
multipliers per device, divide the total number of 9 × 9-bit multipliers by 8.  
Altera Corporation  
July 2005  
1–3  
Stratix Device Handbook, Volume 1  
 
 
 
 
 
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