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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Operating Conditions  
Table 4–2. Stratix Device Recommended Operating Conditions (Part 2 of 2)  
Symbol  
Parameter  
Conditions  
Minimum  
Maximum  
Unit  
VCCIO  
Supply voltage for output  
buffers, 3.3-V operation  
(4), (5)  
3.00 (3.135)  
3.60 (3.465)  
V
Supply voltage for output  
buffers, 2.5-V operation  
(4)  
2.375  
1.71  
1.4  
2.625  
1.89  
1.6  
V
V
V
Supply voltage for output  
buffers, 1.8-V operation  
(4)  
Supply voltage for output  
buffers, 1.5-V operation  
(4)  
VI  
Input voltage  
(3), (6)  
–0.5  
0
4.0  
VCCIO  
85  
V
V
VO  
TJ  
Output voltage  
Operating junction  
temperature  
For commercial use  
For industrial use  
0
°C  
°C  
–40  
100  
Table 4–3. Stratix Device DC Operating Conditions Note (7) (Part 1 of 2)  
Symbol  
Parameter  
Conditions  
Minimum  
Typical  
Maximum  
Unit  
II  
Input pin leakage  
current  
VI = VCCIOmax to 0 V (8)  
–10  
10  
μA  
IOZ  
Tri-stated I/O pin  
leakage current  
VO = VCCIOmax to 0 V (8)  
–10  
10  
μA  
ICC0  
VCC supply current VI = ground, no load, no  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
(standby) (All  
toggling inputs  
memory blocks in  
power-down mode)  
EP1S10. VI = ground, no  
load, no toggling inputs  
37  
65  
EP1S20. VI = ground, no  
load, no toggling inputs  
EP1S25. VI = ground, no  
load, no toggling inputs  
90  
EP1S30. VI = ground, no  
load, no toggling inputs  
114  
145  
200  
277  
EP1S40. VI = ground, no  
load, no toggling inputs  
EP1S60. VI = ground, no  
load, no toggling inputs  
EP1S80. VI = ground, no  
load, no toggling inputs  
4–2  
Altera Corporation  
January 2006  
Stratix Device Handbook, Volume 1  
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