Stratix Architecture
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out. Figure 2–63 illustrates the control signal
selection.
Figure 2–63. Control Signal Selection per IOE
io_bclk[3..0]
io_bce[3..0]
io_bclr[3..0]
io_boe[3..0]
Dedicated I/O
Clock [7..0]
I/O Interconnect
[15..0]
io_coe
Local
Interconnect
io_cclr
Local
Interconnect
io_cce_out
Local
Interconnect
io_cce_in
io_cclk
Local
Interconnect
ce_out
clk_out
sclr/preset
Local
Interconnect
clk_in
ce_in
aclr/preset
oe
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and row interconnects. Figure 2–64
shows the IOE in bidirectional configuration.
Altera Corporation
July 2005
2–109
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
