ACEX 1K Programmable Logic Device Family Data Sheet
Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tR
Input rise time
Input fall time
Input duty cycle
5
5
ns
ns
tF
tINDUTY
fCLK1
40
25
60
80
%
Input clock frequency (ClockBoost clock
multiplication factor equals 1)
MHz
fCLK2
Input clock frequency (ClockBoost clock
multiplication factor equals 2)
16
40
MHz
fCLKDEV
Input deviation from user specification in
25,000 PPM
the software (1)
tINCLKSTB Input clock stability (measured between
100
10
ps
adjacent clocks)
tLOCK
Time required for ClockLock or ClockBoost
µs
to acquire lock (3)
tJITTER
Jitter on ClockLock or ClockBoost-
tINCLKSTB < 100
tINCLKSTB < 50
250 (4)
200 (4)
60
ps
ps
%
generated clock (4)
13
tOUTDUTY Duty cycle for ClockLock or ClockBoost-
40
50
generated clock
Notes to tables:
(1) To implement the ClockLock and ClockBoost circuitry with the Altera software, designers must specify the input
frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The
f
parameter specifies how much the incoming clock can differ from the specified frequency during device
CLKDEV
operation. Simulation does not reflect this parameter.
(2) Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3) During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the t
value is less than the time required for configuration.
LOCK
(4) The t
specification is measured under long-term observation. The maximum value for t
is 200 ps if
JITTER
JITTER
t
is lower than 50 ps.
INCLKSTB
This section discusses the PCI pull-up clamping diode option, slew-rate
control, open-drain output option, and MultiVolt I/ O interface for
ACEX 1K devices. The PCI pull-up clamping diode, slew-rate control, and
open-drain output options are controlled pin-by-pin via Altera software
logic options. The MultiVolt I/ O interface is controlled by connecting
VCCIO to a different voltage than VCCINT. Its effect can be simulated in the
Altera software via the Global Project Device Options dialog box (Assign
menu).
I/O
Configuration
Altera Corporation
39
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