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EP1K50QC208-3N 参数 Datasheet PDF下载

EP1K50QC208-3N图片预览
型号: EP1K50QC208-3N
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件
文件页数/大小: 86 页 / 1204 K
品牌: ALTERA [ ALTERA CORPORATION ]
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ACEX 1K Programmable Logic Device Family Data Sheet  
PCI Pull-Up Clamping Diode Option  
ACEX 1K devices have a pull-up clamping diode on every I/ O, dedicated  
input, and dedicated clock pin. PCI clamping diodes clamp the signal to  
the VCCIO value and are required for 3.3-V PCI compliance. Clamping  
diodes can also be used to limit overshoot in other systems.  
Clamping diodes are controlled on a pin-by-pin basis. When VCCIO is  
3.3 V, a pin that has the clamping diode option turned on can be driven by  
a 2.5-V or 3.3-V signal, but not a 5.0-V signal. When VCCIO is 2.5 V, a pin  
that has the clamping diode option turned on can be driven by a 2.5-V  
signal, but not a 3.3-V or 5.0-V signal. Additionally, a clamping diode can  
be activated for a subset of pins, which allows a device to bridge between  
a 3.3-V PCI bus and a 5.0-V device.  
Slew-Rate Control  
The output buffer in each IOE has an adjustable output slew rate that can  
be configured for low-noise or high-speed performance. A slower slew  
rate reduces system noise and adds a maximum delay of 4.3 ns. The fast  
slew rate should be used for speed-critical outputs in systems that are  
adequately protected against noise. Designers can specify the slew rate  
pin-by-pin or assign a default slew rate to all pins on a device-wide basis.  
The slow slew rate setting affects only the falling edge of the output.  
Open-Drain Output Option  
ACEX 1K devices provide an optional open-drain output (electrically  
equivalent to open-collector output) for each I/ O pin. This open-drain  
output enables the device to provide system-level control signals (e.g.,  
interrupt and write enable signals) that can be asserted by any of several  
devices. It can also provide an additional wired-ORplane.  
MultiVolt I/O Interface  
The ACEX 1K device architecture supports the MultiVolt I/ O interface  
feature, which allows ACEX 1K devices in all packages to interface with  
systems of differing supply voltages. These devices have one set of VCC  
pins for internal operation and input buffers (VCCINT), and another set for  
I/ O output drivers (VCCIO).  
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Altera Corporation  
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