ACEX 1K Programmable Logic Device Family Data Sheet
Figure 31. ACEX 1K ICCACTIVE vs. Operating Frequency
EP1K30
EP1K50
100
80
60
40
20
200
150
100
ICC Supply
Current (mA)
ICC Supply
Current (mA)
50
0
0
100
100
50
50
Frequency (MHz)
Frequency (MHz)
EP1K100
300
200
100
ICC Supply
Current (mA)
13
0
100
50
Frequency (MHz)
The ACEX 1K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Configuration &
Operation
Operating Modes
The ACEX 1K architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. Before configuration, as VCC rises, the device initiates a
Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The ACEX 1K POR time does not exceed 50 µs.
1
When configuring with a configuration device, refer to the
relevant configuration device data sheet for POR timing
information.
Altera Corporation
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