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Functional Description
Fast Passive Parallel Configuration
Stratix series and APEX II devices can be configured using the EPC device in the FPP
configuration mode. In this mode, the EPC device sends a byte of data on the
DATA[7..0]
pins, which connect to the
DATA[7..0]
input pins of the FPGA, per
DCLK
cycle. Stratix series and APEX II FPGAs receive byte-wide configuration data per
DCLK
cycle.
shows the EPC device in FPP configuration mode. In this figure, the
external flash interface is not used and hence most flash pins are left unconnected
(with the few noted exceptions).
f
For more information about configuration interface connections including the pull-up
resistor values, supply voltages, and
MSEL
pin settings, refer to the configuration
chapter in the appropriate device handbook.
Figure 2. FPP Configuration
V
CC
(1)
V
CC
(1)
Stratix Series
or
APEX II Device
n
(6)
MSEL
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
(1)
V
CC
N.C.
nCEO
nCE
EPC Device
(3)
(3)
WE#C
WE#F
RP#C
RP#F
DCLK
A[20..0]
DATA[7..0]
OE
(3)
RY/BY#
nCS
(3)
CE#
nINIT_CONF
(2)
OE#
DQ[15..0]
WP#
BYTE#
(5)
TM1
V
CC
(7)
VCCW
PORSEL
PGM[2..0]
TMO
EXCLK
(4)
(4)
(4)
N.C.
N.C.
N.C.
N.C.
N.C.
GND
GND
C-A0
(5)
C-A1
(5)
C-A15
(5)
C-A16
(5)
A0-F
A1-F
A15-F
A16-F
Notes to
(1) The V
CC
should be connected to the same supply voltage as the EPC device.
(2) The
nINIT_CONF
pin is available on EPC devices and has an internal pull-up resistor that is always active. This means an external pull-up
resistor is not required on the
nINIT_CONF
or
nCONFIG
signal. The
nINIT_CONF
pin does not need to be connected if its functionality is not
used. If
nINIT_CONF
is not used,
nCONFIG
must be pulled to V
CC
either directly or through a resistor.
(3) The EPC devices’
OE
and
nCS
pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external pull-up resistors
should not be used on these pins. The internal pull-up resistors are used by default in the Quartus
II software. To turn off the internal pull-up
resistors, check the
Disable nCS and OE pull-ups on configuration device
option when generating programming files.
(4) For
PORSEL, PGM[],
and
EXCLK
pin connections, refer to
(5) In the 100-pin PQFP package, you must externally connect the following pins:
C-A0
to
F-A0, C-A1
to
F-A1, C-A15
to
F-A15, C-A16
to
F-A16,
and
BYTE#
to V
CC
. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages:
C-RP#
to
F-RP#, C-WE#
to
F-WE#, TM1
to V
CC
,
TM0
to GND, and
WP#
to V
CC
.
(6) Connect the FPGA
MSEL[]
input pins to select the FPP configuration mode. For more information, refer to the configuration chapter in the
appropriate device handbook.
(7) To protect Intel Flash-based EPC devices content, isolate the V
CCW
supply from V
CC
. For more information, refer to
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
