Functional Description
Page 9
Finally, the configuration controller also manages errors during configuration. A
CONF_DONE
error occurs when the FPGA does not de-assert its
CONF_DONE
signal within
64
DCLK
cycles after the last bit of configuration data is transmitted. When a
CONF_DONE
error is detected, the controller pulses the
OE
line low, which pulls the
nSTATUS
signal
low and triggers another configuration cycle.
A cyclic redundancy check (CRC) error occurs when the FPGA detects corruption in
the configuration data. This corruption could be a result of noise coupling on the
board such as poor signal integrity on the configuration signals. When this error is
signaled by the FPGA (by driving the
nSTATUS
signal low), the controller stops
configuration. If the
Auto-Restart Configuration After Error
option is enabled in the
FPGA, it releases its
nSTATUS
signal after a reset time-out period and the controller
attempts to reconfigure the FPGA.
After the FPGA configuration process is complete, the controller drives the
DCLK
pin
low and the
DATA[]
pins high. Additionally, the controller tri-states its internal
interface to the flash memory, enables the weak internal pull-ups on the flash address
and control lines, and enables bus-keep circuits on flash data lines.
The following sections describe the different configuration schemes supported by the
EPC device—FPP, PS, and concurrent configuration schemes.
f
For more information, refer to the configuration chapter in the appropriate device
handbook.
Configuration Signals
lists the configuration signal connections between the EPC device and Altera
FPGAs.
Table 4. Configuration Signals
EPC Device Pin
DATA[]
DCLK
Altera FPGA Pin
DATA[]
DCLK
Description
Configuration data transmitted from the EPC device to the
FPGA, which is latched on the rising edge of
DCLK.
EPC device generated clock used by the FPGA to latch
configuration data provided on the
DATA[]
pins.
Open-drain output from the EPC device that is used to
start FPGA reconfiguration using the initiate configuration
(INIT_CONF) JTAG instruction. This connection is not
needed if the
INIT_CONF
JTAG instruction is not needed.
If
n
INIT
_
CONF
is not connected to
nCONFIG, nCONFIG
must be tied to V
CC
either directly or through a pull-up
resistor.
Open-drain bidirectional configuration status signal,
which is driven low by either the EPC device or FPGA
during POR and to signal an error during configuration.
Low pulse on
OE
resets the EPC device controller.
Configuration done output signal driven by the FPGA.
nINIT_CONF,
which
nCONFIG
OE
nSTATUS
nCS
CONF_DONE
January 2012
Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet
ALTERA [ ALTERA CORPORATION ]
