Preliminary Information
Cyclone FPGA Family Data Sheet
Tables 53 through 54 show the external timing parameters on column and
row pins for EP1C6 devices.
Table 53. EP1C6 Column Pin Global Clock External I/O Timing Parameters
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.432
0.000
2.000
2.643
0.000
2.000
2.853
0.000
2.000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
3.720
5.347
5.347
4.121
5.912
5.912
4.527
6.480
6.480
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
1.188
0.000
0.500
3.534
3.534
1.301
0.000
0.500
3.892
3.892
1.414
0.000
0.500
4.251
4.251
1.907
2.101
2.298
Table 54. EP1C6 Row Pin Global Clock External I/O Timing Parameters
Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.517
0.000
2.000
2.741
0.000
2.000
2.966
0.000
2.000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
3.618
5.204
5.204
4.004
5.749
5.749
4.394
6.298
6.298
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
1.273
0.000
0.500
3.391
3.391
1.399
0.000
0.500
3.729
3.729
1.527
0.000
0.500
4.069
4.069
1.805
1.984
2.165
Altera Corporation
83
ALTERA [ ALTERA CORPORATION ]
