Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 38. External Timing in Cyclone Devices
OE Register
PRN
D
Q
t
t
t
t
t
XZ
Dedicated
Clock
ZX
INSU
INH
CLRN
OUTCO
Output Register
PRN
Bidirectional
Pin
D
Q
CLRN
Input Register
PRN
D
Q
CLRN
All external I/O timing parameters shown are for 3.3-V LVTTL I/O
standard with the maximum current strength and fast slew rate. For
external I/O timing using standards other than LVTTL or for different
current strengths, use the I/O standard input and output delay adders in
Tables 59 through 63.
Altera Corporation
79
ALTERA [ ALTERA CORPORATION ]
