Cyclone Device Handbook, Volume 1
Figure 4–2. External Timing in Cyclone Devices
OE Register
PRN
D
Q
t
t
t
t
t
XZ
ZX
INSU
INH
OUTCO
Dedicated
Clock
CLRN
Output Register
PRN
Bidirectional
Pin
D
Q
CLRN
Input Register
PRN
D
Q
CLRN
All external I/O timing parameters shown are for 3.3-V LVTTL I/O
standard with the maximum current strength and fast slew rate. For
external I/O timing using standards other than LVTTL or for different
current strengths, use the I/O standard input and output delay adders in
Tables 4–40 through 4–44.
Table 4–29 shows the external I/O timing parameters when using global
clock networks.
Table 4–29. Cyclone Global Clock External I/O Timing Parameters
Notes (1), (2) (Part 1 of 2)
Symbol
Parameter
Conditions
tINSU
Setup time for input or bidirectional pin using IOE input
register with global clock fed by CLKpin
tINH
Hold time for input or bidirectional pin using IOE input
register with global clock fed by CLKpin
tOUTCO
tINSUPLL
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock fed by CLKpin
CLOAD = 10 pF
Setup time for input or bidirectional pin using IOE input
register with global clock fed by Enhanced PLL with default
phase setting
tINHPLL
Hold time for input or bidirectional pin using IOE input
register with global clock fed by enhanced PLL with default
phase setting
4–16
Preliminary
Altera Corporation
January 2007
ALTERA [ ALTERA CORPORATION ]
