Cyclone Device Handbook, Volume 1
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 4–25 through 4–28 show the
internal timing microparameters for LEs, IOEs, TriMatrix memory
structures, DSP blocks, and MultiTrack interconnects.
Table 4–25. LE Internal Timing Microparameters
-6
-7
-8
Symbol
Unit
Min
29
Max
Min
33
Max
Min
37
Max
tSU
ps
ps
ps
ps
ps
ps
ps
tH
12
13
15
tCO
tLUT
tCLR
tPRE
173
454
198
522
224
590
129
129
148
148
167
167
tCLKHL
1,234
1,562
1,818
Table 4–26. IOE Internal Timing Microparameters
-6 -7
-8
Symbol
Unit
Min
348
0
Max
Min
400
0
Max
Min
452
0
Max
tSU
tH
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tCO
511
587
664
tPIN2COMBOUT_R
tPIN2COMBOUT_C
tCOMBIN2PIN_R
tCOMBIN2PIN_C
tCLR
1,130
1,135
2,627
2,615
1,299
1,305
3,021
3,007
1,469
1,475
3,415
3,399
280
280
322
322
364
364
tPRE
tCLKHL
1,234
1,562
1,818
4–14
Preliminary
Altera Corporation
January 2007
ALTERA [ ALTERA CORPORATION ]
