Timing Model
Table 4–39. EP1C20 Row Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.417
0.000
2.000
2.779
0.000
2.000
3.140
0.000
2.000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
3.724
3.645
3.645
4.282
4.191
4.191
4.843
4.740
4.740
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
1.417
0.000
0.500
1.629
0.000
0.500
1.840
0.000
0.500
1.667
1.588
1.588
1.917
1.826
1.826
2.169
2.066
2.066
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output
adders and programmable input and output delays are specified by
speed grade independent of device density.
Tables 4–40 through 4–45 show the adder delays associated with column
and row I/O pins for all packages. If an I/O standard is selected other
than LVTTL 4 mA with a fast slew rate, add the selected delay to the
external tCO and tSU I/O parameters shown in Tables 4–25 through
4–28.
Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 1 of 2)
-6 Speed Grade -7 Speed Grade -8 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
0
0
0
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
0
0
0
27
31
35
182
278
−250
−250
−278
209
319
−288
−288
−320
236
361
−325
−325
−362
Altera Corporation
January 2007
4–21
Preliminary
ALTERA [ ALTERA CORPORATION ]
