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EP1C4F324I7ES 参数 Datasheet PDF下载

EP1C4F324I7ES图片预览
型号: EP1C4F324I7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1360 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1  
Table 4–22. IOE Internal Timing Microparameter Descriptions  
Symbol  
Parameter  
tSU  
IOE input and output register setup time before clock  
IOE input and output register hold time after clock  
IOE input and output register clock-to-output delay  
Row input pin to IOE combinatorial output  
Column input pin to IOE combinatorial output  
Row IOE data input to combinatorial output pin  
Column IOE data input to combinatorial output pin  
Minimum clear pulse width  
tH  
tCO  
tPIN2COMBOUT_R  
tPIN2COMBOUT_C  
tCOMBIN2PIN_R  
tCOMBIN2PIN_C  
tCLR  
tPRE  
Minimum preset pulse width  
tCLKHL  
Minimum clock high or low time  
Table 4–23. M4K Block Internal Timing Microparameter Descriptions  
Symbol Parameter  
tM4KRC  
Synchronous read cycle time  
tM4KWC  
Synchronous write cycle time  
tM4KWERESU  
tM4KWEREH  
tM4KBESU  
Write or read enable setup time before clock  
Write or read enable hold time after clock  
Byte enable setup time before clock  
Byte enable hold time after clock  
tM4KBEH  
tM4KDATAASU  
tM4KDATAAH  
tM4KADDRASU  
tM4KADDRAH  
tM4KDATABSU  
tM4KDATABH  
tM4KADDRBSU  
tM4KADDRBH  
tM4KDATACO1  
tM4KDATACO2  
tM4KCLKHL  
tM4KCLR  
A port data setup time before clock  
A port data hold time after clock  
A port address setup time before clock  
A port address hold time after clock  
B port data setup time before clock  
B port data hold time after clock  
B port address setup time before clock  
B port address hold time after clock  
Clock-to-output delay when using output registers  
Clock-to-output delay without output registers  
Minimum clock high or low time  
Minimum clear pulse width  
4–12  
Preliminary  
Altera Corporation  
January 2007  
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