Cyclone Device Handbook, Volume 1
Performance
The maximum internal logic array clock tree frequency is limited to the
specifications shown in Table 4–19.
Table 4–19. Clock Tree Maximum Performance Specification
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Parameter
Definition
Units
Min Typ Max Min Typ Max Min Typ Max
Clock tree
fMAX
Maximumfrequency
that the clock tree
can support for
clocking registered
logic
405
320
275 MHz
Table 4–20 shows the Cyclone device performance for some common
designs. All performance values were obtained with the Quartus II
software compilation of library of parameterized modules (LPM)
functions or megafunctions. These performance values are based on
EP1C6 devices in 144-pin TQFP packages.
Table 4–20. Cyclone Device Performance
Resources Used
M4K
Performance
Resource
Used
Design Size &
Function
M4K
-6 Speed -7 Speed -8 Speed
Mode
LEs
Memory Memory
Grade
(MHz)
Grade
(MHz)
Grade
(MHz)
Bits
Blocks
LE
16-to-1
multiplexer
-
-
21
44
-
-
405.00
320.00
275.00
32-to-1
-
-
317.36
284.98
260.15
multiplexer
16-bit counter
-
-
16
66
-
-
-
-
405.00
208.99
320.00
181.98
275.00
160.75
64-bit counter (1)
4–10
Preliminary
Altera Corporation
January 2007
ALTERA [ ALTERA CORPORATION ]
