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EP1C4F324I7ES 参数 Datasheet PDF下载

EP1C4F324I7ES图片预览
型号: EP1C4F324I7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1360 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1  
of the standard. Using minimum settings provides signal slew rate  
control to reduce system noise and signal overshoot. Table 2–11 shows the  
possible settings for the I/O standards with drive strength control.  
Table 2–11. Programmable Drive Strength Note (1)  
IOH/IOL Current Strength Setting (mA)  
I/O Standard  
LVTTL (3.3 V)  
4
8
12  
16  
24(2)  
2
LVCMOS (3.3 V)  
LVTTL (2.5 V)  
4
8
12(2)  
2
8
12  
16(2)  
2
LVTTL (1.8 V)  
8
12(2)  
2
LVCMOS (1.5 V)  
4
8(2)  
Notes to Table 2–11:  
(1) SSTL-3 class I and II, SSTL-2 class I and II, and 3.3-V PCI I/O Standards do not  
support programmable drive strength.  
(2) This is the default current strength setting in the Quartus II software.  
Open-Drain Output  
Cyclone devices provide an optional open-drain (equivalent to an open-  
collector) output for each I/O pin. This open-drain output enables the  
device to provide system-level control signals (e.g., interrupt and write-  
enable signals) that can be asserted by any of several devices.  
2–50  
Preliminary  
Altera Corporation  
January 2007  
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