I/O Structure
Figure 2–34. DDR SDRAM & FCRAM Interfacing
DQS
OE LE
Register
OE
DQ
OE
OE LE
Output LE
Register
Register
OE LE
Register
V
CC
Output LE
Registers
t
Δ
clk
Adjacent
LAB LEs
OE LE
Register
Input LE
Registers
DataA
DataB
Output LE
Register
-90˚ clk
GND
Output LE
Registers
Input LE
Registers
Programmable
Delay Chain
PLL
Global Clock
Phase Shifted -90˚
LE
Register
LE
Register
Resynchronizing
Global Clock
Adjacent LAB LEs
Programmable Drive Strength
The output buffer for each Cyclone device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standards have several levels of drive strength that the designer
can control. SSTL-3 class I and II, and SSTL-2 class I and II support a
minimum setting, the lowest drive strength that guarantees the IOH/IOL
Altera Corporation
January 2007
2–49
Preliminary
ALTERA [ ALTERA CORPORATION ]
