Cyclone FPGA Family Data Sheet
Preliminary Information
Tables 51 through 52 show the external timing parameters on column and
row pins for EP1C4 devices.
Table 51. EP1C4 Column Pin Global Clock External I/O Timing Parameters (1)
Symbol
-6 Speed Grade
Min Max
-7 Speed Grade
Min Max
-8 Speed Grade
Min Max
Unit
tINSU
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
Table 52. EP1C4 Row Pin Global Clock External I/O Timing Parameters (1)
Symbol
-6 Speed Grade
Min Max
-7 Speed Grade
Min Max
-8 Speed Grade
Min Max
Unit
tINSU
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
Note to Tables 51 and 52:
(1) Contact Altera Applications for EP1C4 device timing parameters.
82
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
