Cyclone FPGA Family Data Sheet
Preliminary Information
Table 46. M4K Block Internal Timing Microparameters
Symbol -6 -7
-8
Unit
Min
Max
Min
Max
Min
Max
tM4KRC
4,379
2,910
5,035
3,346
5,691
3,783
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tM4KWC
tM4KWERESU
tM4KWEREH
tM4KBESU
72
43
72
43
72
43
72
43
72
43
72
43
82
49
82
49
82
49
82
49
82
49
82
49
93
55
93
55
93
55
93
55
93
55
93
55
tM4KBEH
tM4KDATAASU
tM4KDATAAH
tM4KADDRASU
tM4KADDRAH
tM4KDATABSU
tM4KDATABH
tM4KADDRBSU
tM4KADDRBH
tM4KDATACO1
tM4KDATACO2
tM4KCLKHL
tM4KCLR
621
714
807
4,351
5,003
5,656
105
286
120
328
136
371
Table 47. Routing Delay Internal Timing Microparameters
Symbol -6 -7
-8
Unit
Min
Max
Min
Max
Min
Max
tR4
tC4
tLOCAL
261
338
244
300
388
281
339
439
318
ps
ps
ps
External Timing Parameters
External timing parameters are specified by device density and speed
grade. Figure 38 shows the timing model for bidirectional IOE pin timing.
All registers are within the IOE.
78
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
