Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 24. I/O Clock Regions
Column I/O Clock Region
IO_CLK[5..0]
6
I/O Clock Regions
Cyclone Logic Array
LAB Row Clocks
labclk[5..0]
LAB Row Clocks
labclk[5..0]
6
6
6
LAB Row Clocks
labclk[5..0]
LAB Row Clocks
labclk[5..0]
6
Global Clock
Network
8
Row
I/O Regions
LAB Row Clocks
labclk[5..0]
LAB Row Clocks
labclk[5..0]
6
6
I/O Clock Regions
6
Column I/O Clock Region
IO_CLK[5..0]
PLLs
Cyclone PLLs provide general-purpose clocking with clock multiplication
and phase shifting as well as outputs for differential I/O support. Cyclone
devices contain two PLLs, except for the EP1C3 device, which contains
one PLL.
Altera Corporation
37
ALTERA [ ALTERA CORPORATION ]
