Cyclone FPGA Family Data Sheet
Preliminary Information
Figure 19. Input/Output Clock Mode in Simple Dual-Port Mode
Note (1)
6 LAB Row
Clocks
Memory Block
256 ´ 16
6
data[ ]
address[ ]
byteena[ ]
D
ENA
Q
Q
Q
Data In
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Read Address
D
ENA
To MultiTrack
Interconnect
Data Out
Byte Enable
D
Q
ENA
D
ENA
wraddress[ ]
rden
Write Address
Read Enable
D
ENA
Q
Q
D
ENA
wren
outclken
Write
Pulse
Generator
D
ENA
Q
Write Enable
inclken
inclock
outclock
Note to Figures 19:
(1) All registers shown except the rden register have asynchronous clear ports.
Read/Write Clock Mode
The M4K memory blocks implement read/write clock mode for simple
dual-port memory. The designer can use up to two clocks in this mode.
The write clock controls the block’s data inputs, wraddress, and wren.
The read clock controls the data output, rdaddress, and rden. The
memory blocks support independent clock enables for each clock and
asynchronous clear signals for the read- and write-side registers.
Figure 20 shows a memory block in read/write clock mode.
32
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
