Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 15. M4K RAM Block Control Signals
Dedicated
LAB Row
Clocks
6
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
alcr_a
clocken_a
renwe_b
clock_b
Local
Local
Interconnect
Interconnect
clock_a
renwe_a
alcr_b
clocken_b
Figure 16. M4K RAM Block LAB Row Interface
C4 Interconnects
R4 Interconnects
10
Direct link
Direct link
interconnect
to adjacent LAB
interconnect
to adjacent LAB
dataout
M4K RAM
Block
Direct link
Direct link
interconnect
interconnect
from adjacent LAB
from adjacent LAB
Byte enable
Clocks
Control
Signals
address
datain
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
Altera Corporation
29
ALTERA [ ALTERA CORPORATION ]
