4–78
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–77 lists column pin delay adders when using the regional clock in Arria GX
devices.
Table 4–77. EP1AGX90 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed Grade
Units
Industrial
0.138
Commercial
0.138
RCLK input adder
0.354
–3.607
–0.353
5.188
ns
ns
ns
ns
RCLK PLL input adder
RCLKoutput adder
–1.697
–0.138
1.966
–1.697
–0.138
RCLK PLL output adder
1.966
Dedicated Clock Pin Timing
Table 4–79 through Table 4–98 list clock pin timing for Arria GX devices when the
clock is driven by the global clock, regional clock, periphery clock, and a PLL.
Table 4–78 lists Arria GX clock timing parameters.
Table 4–78. Arria GX Clock Timing Parameters
Symbol
Parameter
tCIN
Delay from clock pad to I/O input register
Delay from clock pad to I/O output register
Delay from PLL inclkpad to I/O input register
Delay from PLL inclkpad to I/O output register
tCOUT
tPLLCIN
tPLLCOUT
EP1AGX20 Clock Timing Parameters
Table 4–79 through Table 4–80 list the GCLKclock timing parameters for EP1AGX20
devices.
Table 4–79 lists clock timing specifications.
Table 4–79. EP1AGX20 Row Pins Global Clock Timing Parameters
Fast Model
Parameter
tcin
–6 Speed Grade
Units
Industrial
1.394
Commercial
1.394
3.161
3.155
0.091
0.085
ns
ns
ns
ns
tcout
1.399
1.399
tpllcin
tpllcout
–0.027
–0.022
–0.027
–0.022
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
