Chapter 4: DC and Switching Characteristics
4–77
Typical Design Performance
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 4 of 4)
Fast Corner
Drive
Strength
–6 Speed
Grade
I/O Standard
Clock
Parameter
Units
Industrial
2.845
0.783
2.839
0.777
2.826
0.764
2.829
0.767
2.831
0.769
2.987
0.923
2.987
0.923
3.835
1.769
Commercial
2.845
0.783
2.839
0.777
2.826
0.764
2.829
0.767
2.831
0.769
2.987
0.923
2.987
0.923
3.835
1.769
1.5-V HSTL
CLASS I
10 mA
12 mA
16 mA
18 mA
20 mA
—
GCLK
GCLK PLL
GCLK
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
6.264
2.133
6.262
2.131
6.074
1.943
6.084
1.953
6.097
1.966
6.414
2.279
6.414
2.279
7.541
3.404
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5-V HSTL
CLASS I
GCLK PLL
GCLK
1.5-V HSTL
CLASS II
GCLK PLL
GCLK
1.5-V HSTL
CLASS II
GCLK PLL
GCLK
1.5-V HSTL
CLASS II
GCLK PLL
GCLK
3.3-V PCI
3.3-V PCI-X
LVDS
GCLK PLL
GCLK
—
GCLK PLL
GCLK
—
GCLK PLL
Table 4–76 through Table 4–77 list the EP1AGX90 regional clock (RCLK) adder values
that should be added to the GCLKvalues. These adder values are used to determine
I/O timing when the I/O pin is driven using the regional clock. This applies for all
I/O standards supported by Arria GX with general purpose I/O pins.
Table 4–76 lists row pin delay adders when using the regional clock in Arria GX
devices.
Table 4–76. EP1AGX90 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed Grade
Units
Industrial
0.175
Commercial
0.175
RCLK input adder
0.418
0.015
ns
ns
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
0.007
0.007
–0.175
–0.007
–0.175
–0.007
–0.418
–0.015
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
