Arria GX Device Family Overview
across densities, the designer must cross-reference the available I/O pins
using the device pin-outs for all planned densities of a given package type
to identify which I/O pins are migratable.
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels)
Source-Synchronous
Channels
Receive
EP1AGX20C
EP1AGX35C
EP1AGX50C
EP1AGX60C
EP1AGX35D
EP1AGX50D
EP1AGX60D
EP1AGX60E
EP1AGX90E
4
4
4
4
8
8
8
12
12
31
31
31
31
31
31, 42
31
42
47
Maximum User I/O Pin Count
484-Pin FBGA
(23 mm)
230
230
229
229
—
—
—
—
—
Device
Transceiver
Channels
Transmit
29
29
29
29
29
29, 42
29
42
45
780-Pin FBGA 1152-Pin FBGA
(29 mm)
(35 mm)
341
—
—
—
341
350
350
—
—
—
—
—
—
—
514
—
514
538
lists the Arria GX device package sizes.
Table 1–3. Arria GX FBGA Package Sizes
Dimension
Pitch (mm)
Area (mm
2
)
Length × width
(mm × mm)
484 Pins
1.00
529
23 × 23
780 Pins
1.00
841
29 × 29
1152 Pins
1.00
1225
35 × 35
1–4
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
