FLEX 10K Embedded Programmable Logic Family Data Sheet
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For more information, see the following documents:
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Configuration Devices for APEX & FLEX Devices Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlaster Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
Application Note 59 (Configuring FLEX 10K Devices)
FLEX 10K devices are supported by Quartus and MAX+PLUS II
development systems; a single, integrated package that offers schematic,
text (including AHDL), and waveform design entry, compilation and
logic synthesis, full simulation and worst-case timing analysis, and device
configuration. The Quartus and MAX+PLUS II software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX workstation-based EDA tools.
The Quartus and MAX+PLUS II software works easily with common gate
array EDA tools for synthesis and simulation. For example, the
MAX+PLUS II software can generate Verilog HDL files for simulation
with tools such as Cadence Verilog-XL. Additionally, the Quartus and
MAX+PLUS II software contains EDA libraries that use device-specific
features such as carry chains which are used for fast counter and
arithmetic functions. For instance, the Synopsys Design Compiler library
supplied with the Quartus and MAX+PLUS II development systems
include DesignWare functions that are optimized for the FLEX 10K
architecture.
The MAX+PLUS II development system runs on Windows-based PCs and
Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations, and the Quartus development system runs on Windows-
based PCs and Sun SPARCstation and HP 9000 Series 700 workstations.
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Functional
Description
See the
MAX+PLUS II Programmable Logic Development System & Software
Data Sheet
for more information.
Each FLEX 10K device contains an embedded array to implement
memory and specialized logic functions, and a logic array to implement
general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 2,048 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions, such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
Altera Corporation
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ALTERA [ ALTERA CORPORATION ]
