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DPCLK3 参数 Datasheet PDF下载

DPCLK3图片预览
型号: DPCLK3
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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5–10  
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
Cyclone III Device Family PLL Hardware Overview  
Cyclone III Device Family PLL Hardware Overview  
This section gives a hardware overview of the Cyclone III device family PLL.  
Figure 5–6 shows a simplified block diagram of the major components of the PLL of  
the Cyclone III device family.  
(1)  
Figure 5–6. Cyclone III Device Family PLL Block Diagram  
lock  
LOCK  
circuit  
÷C0  
÷C1  
÷C2  
Clock inputs  
from pins  
4
8
÷n  
clkswitch  
8
÷2 (2)  
inclk0  
inclk1  
LF  
VCO  
PFD  
CP  
Clock  
Switchover  
Block  
PLL  
output  
mux  
clkbad0  
GCLKs  
÷C3  
÷C4  
GCLK(3)  
clkbad1  
VCO  
Range  
Detector  
VCOOVRR  
VCOUNDR  
External clock  
output  
activeclock  
pfdena  
÷M  
no compensation;  
ZDB mode  
GCLK  
networks  
source-synchronous;  
normal mode  
Notes to Figure 5–6:  
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.  
(2) This is the VCO post-scale counter K.  
(3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another  
PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.  
1
The VCO post-scale counter K is used to divide the supported VCO range by two. The  
VCO frequency reported by the Quartus II software in the PLL summary section of  
the compilation report takes into consideration the VCO post-scale counter value.  
Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is  
lower than the fVCO specification specified in the Cyclone III Device Data Sheet and  
Cyclone III LS Device Data Sheet chapters.  
External Clock Outputs  
Each PLL of the Cyclone III device family supports one single-ended clock output or  
one differential clock output. Only the C0 output counter can feed the dedicated  
external clock outputs, as shown in Figure 5–7, without going through the GCLK.  
Other output counters can feed other I/O pins through the GCLK.  
Cyclone III Device Handbook  
Volume 1  
July 2012 Altera Corporation  
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