欢迎访问ic37.com |
会员登录 免费注册
发布采购

DPCLK3 参数 Datasheet PDF下载

DPCLK3图片预览
型号: DPCLK3
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号DPCLK3的Datasheet PDF文件第65页浏览型号DPCLK3的Datasheet PDF文件第66页浏览型号DPCLK3的Datasheet PDF文件第67页浏览型号DPCLK3的Datasheet PDF文件第68页浏览型号DPCLK3的Datasheet PDF文件第70页浏览型号DPCLK3的Datasheet PDF文件第71页浏览型号DPCLK3的Datasheet PDF文件第72页浏览型号DPCLK3的Datasheet PDF文件第73页  
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
5–9  
PLLs in the Cyclone III Device Family  
Altera recommends using the clkenasignals when switching the clock source to the  
PLLs or the GCLK. The recommended sequence is:  
1. Disable the primary output clock by deasserting the clkenasignal.  
2. Switch to the secondary clock using the dynamic select signals of the clock control  
block.  
3. Allow some clock cycles of the secondary clock to pass before reasserting the  
clkenasignal. The exact number of clock cycles you must wait before enabling the  
secondary clock is design-dependent. You can build custom logic to ensure glitch-  
free transition when switching between different clock sources.  
PLLs in the Cyclone III Device Family  
The Cyclone III device family offers up to four PLLs that provide robust clock  
management and synthesis for device clock management, external system clock  
management, and high-speed I/O interfaces.  
f
For more information about the number of PLLs in each device density, refer to the  
Cyclone III Device Family Overview chapter.  
The Cyclone III device family PLLs have the same core analog structure.  
Table 5–3 lists the features available in the Cyclone III device family PLLs.  
Table 5–3. Cyclone III Device Family PLL Hardware Features  
Hardware Features  
C (output counters)  
Availability  
5
(1)  
M, N, C counter sizes  
Dedicated clock outputs  
Clock input pins  
1 to 512  
1 single-ended or 1 differential pair  
4 single-ended or 2 differential pairs  
(2)  
Spread-spectrum input clock tracking  
PLL cascading  
v
Through GCLK  
Source-Synchronous Mode, No Compensation  
Mode, Normal Mode, and Zero Delay Buffer Mode  
Compensation modes  
(3)  
Phase shift resolution  
Programmable duty cycle  
Output counter cascading  
Input clock switchover  
User mode reconfiguration  
Loss of lock detection  
Notes to Table 5–3:  
Down to 96-ps increments  
v
v
v
v
v
(1) C counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a  
non-50% duty cycle, the post-scale counters range from 1 through 256.  
(2) Only applicable if the input clock jitter is in the input jitter tolerance specifications.  
(3) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For  
degree increments, the Cyclone III device family can shift all output frequencies in increments of at least 45°.  
Smaller degree increments are possible depending on the frequency and divide parameters.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
 复制成功!