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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
5–19  
Hardware Features  
There are two ways to use the clock switchover feature:  
Use the switchover circuitry for switching from inclk0to inclk1running at the  
same frequency. For example, in applications that require a redundant clock with  
the same frequency as the reference clock, the switchover state machine generates  
a signal that controls the multiplexer select input shown in Figure 5–14. In this  
case, inclk1becomes the reference clock for the PLL. This automatic switchover  
can switch back and forth between the inclk0and inclk1clocks any number of  
times, when one of the two clocks fails and the other clock is available.  
Use the clkswitchinput for user- or system-controlled switch conditions. This is  
possible for same-frequency switchover or to switch between inputs of different  
frequencies. For example, if inclk0is 66 MHz and inclk1is 200 MHz, you must  
control the switchover because the automatic clock-sense circuitry cannot monitor  
primary and secondary clock frequencies with a frequency difference of more than  
20%. This feature is useful when clock sources can originate from multiple cards  
on the backplane, requiring a system-controlled switchover between frequencies  
of operation. Choose the secondary clock frequency so the VCO operates in the  
recommended frequency range. Also, set the M, N, and C counters accordingly to  
keep the VCO operating frequency in the recommended range.  
Figure 5–15 shows a waveform example of the switchover feature when using  
automatic loss of clock detection. Here, the inclk0signal remains low. After the  
inclk0signal remains low for approximately two clock cycles, the clock-sense  
circuitry drives the clkbad[0]signal high. Also, because the reference clock signal is  
not toggling, the switchover state machine controls the multiplexer through the clksw  
signal to switch to inclk1  
.
(1)  
Figure 5–15. Automatic Switchover Upon Clock Loss Detection  
inclk0  
inclk1  
(1)  
muxout  
clkbad0  
clkbad1  
activeclock  
Note to Figure 5–15:  
(1) Switchover is enabled on the falling edge of inclk0or inclk1, depending on which clock is available. In this figure,  
switchover is enabled on the falling edge of inclk1  
.
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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