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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
5–15  
Hardware Features  
Hardware Features  
Cyclone III device family PLLs support several features for general-purpose clock  
management. This section discusses clock multiplication and division  
implementation, phase shifting implementations, and programmable duty cycles.  
Clock Multiplication and Division  
Each Cyclone III device family PLL provides clock synthesis for PLL output ports  
using M/(N*post-scale counter) scaling factors. The input clock is divided by a  
pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop  
drives the VCO to match fIN (M/N). Each output port has a unique post-scale counter  
that divides down the high-frequency VCO. For multiple PLL outputs with different  
frequencies, the VCO value is the least common multiple of the output frequencies  
that meets its frequency specifications. For example, if output frequencies required  
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz  
(the least common multiple of 33 and 66 MHz in the VCO range). Then, the post-scale  
counters scale down the VCO frequency for each output port.  
There is one pre-scale counter, N, and one multiply counter, M, per PLL, with a range  
of 1 to 512 for both M and N. The N counter does not use duty cycle control because  
the purpose of this counter is only to calculate frequency division. There are five  
generic post-scale counters per PLL that can feed GCLKs or external clock outputs.  
These post-scale counters range from 1 to 512 with a 50% duty cycle setting. The  
post-scale counters range from 1 to 256 with any non-50% duty cycle setting. The sum  
of the high/low count values chosen for a design selects the divide value for a given  
counter.  
The Quartus II software automatically chooses the appropriate scaling factors  
according to the input frequency, multiplication, and division values entered into the  
ALTPLL megafunction.  
1
Phase alignment between output counters are determined using the tPLL_PSERR  
specification.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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